Inaugural Lecture - Taming the Complexity of Future Computer Designs
Abstract
Massively parallel and specialized architectures, exemplified by GPUs, have been instrumental in driving several recent scientific breakthroughs, from protein folding to robotics. These machines now handle the majority of the world's computational load. The growing complexity in designing this kind of machine, aimed at meeting the computational needs and opportunities of promising upcoming algorithms, requires tremendous time and effort from engineers to test and validate the new designs. This task, known as verification, is becoming one of the primary challenges in hardware design development. This talk presents techniques I have developed to place verification at the core of computer design, rather than treating verification as an afterthought. I discuss how these techniques could not only improve the development cycle but also provide a solid foundation for establishing clear hardware security guarantees for future computer architectures.
About the speaker
Thomas Bourgeat is a tenure-track Assistant Professor in computer science at EPFL, where he leads the Verification and Computer Architecture Laboratory. His research lies between computer architecture, programming languages and formal methods. He develops techniques to specify, design, and verify the correctness of processors and accelerators. Before starting at EPFL, Thomas Bourgeat studied at MIT under the supervision of Arvind and Adam Chlipala, where he received his PhD degree in 2022.
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